Verilog Source Code Formatter

The VerilogFormatter tool reorganizes Verilog source text files to neatly indent code blocks according to their nesting level. It is a member of SD's family of Source Code Formatters. An example of the Verilog Formatter's results can be seen here.

Verilog Formatter Features

• Formatted code compiles and synthesizes exactly like unformatted code
• Handles full Verilog 2001
• Specification of indentation step distance
• Specification of arbitrary input tab column positions
• A version with obfuscation capability can make it difficult to understand by renaming variables and removing all formatting.

Semantic Designs also offers:

• SystemC Formatter
• SystemVerilog Formatter
• VHDL Formatter

For more information: Info@semanticdesigns.com

Copyright 1995-2010 Semantic Designs, Incorporated
DMS and "Design Maintenance System" are registered trademarks of Semantic Designs, Inc.
The SD logo and "Semantic Designs" are registered service marks of Semantic Designs, Inc.
CloneDR, PARLANSE, JOVIAL2C, Thicket, Smart Differencer are trademarks of Semantic Designs, Inc.
The OMG logo is a registered trademark of the Object Management Group, Inc. in the United States and other countries.
To view our Privacy Policy, click here

Comments or problems: Webmaster@semanticdesigns.com